1. Field of the Invention
The present invention relates to a photosensitive device structure. More particularly, the present invention relates to a photodiode CMOS image sensor.
2. Description of the Related Art
Photodiode CMOS image sensors are common image-sensing devices. A typical photodiode CMOS image sensor includes an array of sensing units and some peripheral logic circuits. Each sensing unit further includes a photodiode, a reset transistor and a read-out transistor. The reset transistor and the read-out transistor are mostly N-type MOS transistors while the logic circuits include both N-type and P-type MOS transistors.
In here, a photodiode CMOS image sensor having N-type heavily doped layer and P-type substrate is used an example. The photodiode is controlled by a logic circuit. A voltage is applied to the gate terminal of a reset transistor. Once the reset transistor is switched on by the logic circuit, the n.sup.+ /p photodiode junction capacitor is charged up so that the n.sup.+ /p photodiode is in reverse bias, thereby forming a large depletion region. When the capacitor is highly charged, the reset transistor is switched off. As light shines on the photosensitive region of the n.sup.+ /p photodiode, electron/hole pairs are generated. The electrons and holes are separated by the electric field in the depletion region. Consequently, electrons move towards the N-doped region and lower the electric potential in the N-doped region. Additionally, holes are drained via the P-type substrate.
To measure the photoelectric signals, another transistor is used to transfer the electrons in the N-doped region to a bus line. Thus, charges produced by the light are directly transmitted to the output terminal for reading without having to pass through any amplification devices. This type of photodiode is often referred to as passive pixel photodiode sensor. In contrast, if the N-doped region is connected to a source follower that includes a transfer transistor, the resulting voltage drop in the gate terminal of the transfer transistor can be used to deduce magnitude of the incoming light. Because the current provided by a source follower is usually large, voltage at the output terminal is rather stable and noise is small. This type of photo-sensor is often referred to as active pixel photodiode sensor.
In recent years, low-cost photodiode CMOS image sensors have often been used as a replacement for expensive charge-coupled device (CCD), active pixel photodiode CMOS image sensors. The reason for this is that active photodiode CMOS image sensor has high quantum efficiency, low read-out noise, high dynamic range and random access property. Furthermore, the manufacturing of active photodiode CMOS image sensor is completely compatible with existing CMOS processes. Therefor, other devices such as control circuits, analogue/digital converters and digital signal processors (DSP) can be integrated on the same silicon chip together with the photodiode to form a so-called system-on-chip (SOC).
In general, a conventional photodiode CMOS image sensor includes at least a PMOS transistor, an NMOS transistor and a P/N junction photodiode. FIGS. 1A through 1F are schematic cross-sectional views showing the progression of steps for producing a conventional photodiode CMOS image sensor.
As shown in FIG. 1A, a P-type substrate 100 is provided. An N-well 110 and a P-well 120 are formed in the substrate 100. A field oxide layer 130 is formed over the N-well 110 so that position of the PMOS active region 140 is marked out. At the same time, field oxide layers 132 and 134 are formed over the P-well 120 to mark out the positions of the NMOS active region 142 and the photodiode active region 144. The field oxide layers 130, 132, 134 all have bird's beak structure on their peripheral region. The field oxide layers 130, 132 and 134 are formed, for example, by local oxidation of silicon (LOCOS).
As shown in FIG. 1B, a gate oxide layer 150a and a gate structure 160a are formed over the PMOS active region 140. At the same time, a gate oxide layer 150b and a gate structure 160b are formed over the NMOS active region 142. A P-type lightly doped drain (LDD) region 170 is formed in the N-well 110 on each side of the gate structure 160a. An N-type lightly doped drain (LDD) region 172a is formed in the P-well 120 on each side of the gate structure 160b. Similarly, an N-type LDD region 172b is formed in the P-well 120 within the photodiode active region 144.
As shown in FIG. 1C, deposition and anisotropic etching are carried out in sequence so that spacers 180a and 180b are formed on the sidewalls of the gate structure 160a and the gate structure 160b respectively. Note that the spacers 180a are regarded as part of the gate structure 160a and the spacers 180b are regarded as part of the gate structure 160b in the subsequent description.
As shown in FIG. 1D, a photoresist layer 185 is formed over the NMOS active region 142 and the photodiode active region 144. Using the photoresist layer 185, the gate structure 160a and the field oxide layer 130 as a mask, an ion implant 187 is carried out to implant P-type ions into the N-well 110. Ultimately, P-type source/drain regions 190 are formed on each side of the gate structure 160a, thereby forming a PMOS transistor 140a.
As shown in FIG. 1E, a photoresist layer 195 is formed over the PMOS transistor 140a. Using the photoresist layer 195, the gate structure 160b, the field oxide layers 132 and 134 as a mask, a second ion implant 197 is carried out to implant N-type ions into the P-well 120. Ultimately, N-type source/drain regions 190a are formed on each side of the gate structure 160b, thereby forming an NMOS transistor 1420a. At the same time, an N-type heavily doped regions 192b is also formed within the photodiode active region 144. This N-type heavily doped region 192b and the P-well 120 beneath the region 192b together constitute a photodiode 144a. Finally, the photoresist layer 195 is removed to form the structure shown in FIG. 1F.
However, the photodiode CMOS image sensor manufactured by the aforementioned method has some problems. As shown in FIG. 1F, the edges of the LOCOS field oxide layer 134 that enclose the photodiode 144a has bird's beak. High stress around the bird's beak region produces some lattice dislocation in the neighborhood of the P-well 120 that may lead to current leaks. In addition, the plasma-etching process for forming the gate structures 160a/160b and spacers 180a/180b (in FIGS. 1B and 1C), the ion implantation for forming the N-type LDD region 172a, the common channel stop implantation, the anti-punchthrough ion implantation and the threshold voltage VT adjusting ion implantation all tend to break up the lattice structure. Hence, dislocation in the photodiode active region 144 close to the field oxide layer 134 can be severe. In other words, current leakage is more likely to occur around this area. With a large current leak, read-out noise of the photodiode CMOS image sensor will increase and image quality will deteriorate.
Moreover, there is an additional problem regarding the aforementioned manufacturing method. Since the NMOS transistor 142a and the photodiode 144a are both on the P-well 120, doping concentration in the P-well 120 must be high for the NMOS transistor 142a to operate normally. Consequently, the junction depletion region between the N-type heavily doped region 192b of the photodiode 144a and the P-well 120 shrinks. Hence, there is a lowering of quantum efficiency of the photodiode 144a (the capacity for transforming optical energy into electrical energy). In other words, the contrast ratio of the photodiode 144a is lower and quality of the image is poor.